`timescale 1ns/100ps

module TEST_Instruction_Register;
	reg [31:0] iInstructionIn;
	reg iIRWrite, iReset, iClk;
	wire [31:0] oInstructionOut;
	
	Instruction_Register U0(.*);
	
	initial begin
	iClk <= 1'b0;
	forever #0.5 iClk <= ~iClk;
	end
	
	initial fork
	#0 {iIRWrite, iInstructionIn, iReset} <= 34'b10101_1;
	#1 iReset <=1'b0;
	#3 iIRWrite <= 1'b1;
	#5 iInstructionIn <= 32'b11001100;
	#6 iIRWrite <= 1'b0;
	#7 iInstructionIn <= 32'b111111;
	#10 iReset<=1'b1;
	#10 iIRWrite<=1'b1;
	#12 iReset<=1'b0;
	join
	
endmodule